Publications

Generating Drug-like Molecules from Gene Expression Signatures using Transformers

Published in Intelligent Systems for Molecular Biology (ISMB) by Sundar Raman P, Prashant G, 2022

Designed a modified transformer architecture to generate many drug-like molecules that can induce a desired transcriptomic profile based on gene-expression signatures. Outperformed then state-of-the-art 2-staged GAN model by ∼40% in validity, uniqueness, ∼30% in synthesizability, ∼10% in similarity metrics of generated molecules. Upon evaluating our model on unseen gene expression signatures (even disease-associated), we observed that the molecules generated by our model are not only similar to the actual compounds to a reasonable extent, but the model also learns certain structural and chemical features that are responsible for specific alterations in gene expression. Find full-paper, code.

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Perturbation Analysis of Practical Algorithms for Maximum Scatter TSP

Published in Symposium on Algorithm Engineering and Experiments (ALENEX22) by Sundar Raman P, Emil Biju, 2022

Proposed six simple-to-code, scalable heuristics for NP-hard Maximum Scatter Travelling Salesman Problem (MSTSP). Studied the reliability of these algorithms in terms of runtime, quality, and stability using smoothed analysis, by slightly perturbing the inputs. Observed practical efficacy of simple heuristics despite their exponential worst-case complexity due to polynomial expected runtime, as the worst-case instances are sparse and rare. Find code.

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Synapse, Systolic CNN Accelerator’s Mapper-Simulator Environment

Published in IIT Madras Bachelor Research Thesis presentation forum by Sundar Raman P, 2021

For ShaktiMAAN, an open-source systolic inference accelerator effort at RISE lab, I designed a python compiler that schedules instructions given network, architecture configuration, and an event-driven, analytical, data-flow accurate simulator. This infrastructure helped address challenges in hardware verification, bottleneck analysis, design-space trade-offs, and compiler optimization for our accelerator. Further, Deep Reinforcement Learning agents (using PPO optimization algorithm) were used along with mapper-simulator to evaluate and explore the design space (tunable hardware/software knobs like buffer-size, loop-order, etc.) of our hardware to map DL networks ∼10% more efficiently than existing heuristics on our hardware. Find slides, code.

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